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MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 1 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 1gbit - 64m x 16 gl-s mirrorbit ? eclipse ? flash memory features ? tin-lead ball metallurgy ? 65 nm mirrorbit eclipse technology ? single supply (v cc ) for read / program / erase (2.7v to 3.6v) ? versatile i/o feature ? wide i/o voltage range (v io ): 1.65v to v cc ? asynchronous 32-byte page read ? 512-byte programming buffer ? programming in page multiples, up to a maximum of 512 bytes ? single word and multiple program on same ? word options ? sector erase ? uniform 128-kbyte sectors ? suspend and resume commands for program and erase operations ? status register, data polling, and ready/busy pin methods to determine device status options marking ? confguration ? 64m x 16 ? fbga package (sn63 pb37 solder) bg ? 64-ball fbga (9mm x 9mm) d ? operating temperature ? industrial (-40c t c +85c) it density voltage range random access time (t acc ) page access time (t pacc ) ce# access time (t ce ) oe# access time (t oe ) 1 gb full v cc = v i0 100 15 100 25 versatileio v io 110 25 110 35 typical program and erase rates buffer programming (512 bytes) 1.5 mb/s sector erase (128 kbytes) 477 kb/s maximum current consumption active read at 5 mhz, 30 pf 60 ma program 100 ma erase 100 ma standby 100 a ? advanced sector protection (asp) ? volatile and non-volatile protection methods for each sector ? separate 1024-byte one time program (otp) array with two lockable regions ? common flash interface (cfi) parameter table ? 100,000 erase cycles for any sector typical ? 20-year data retention typical table 1: performance summary *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 2 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* contents 1 product overview 3 2 address space maps 5 2.1 flash memory array ........................... 7 2.2 device id and cfi (id-cfi) aso ................... 7 2.3 status register aso ........................... 8 2.4 data polling status aso ........................ 8 2.5 secure silicon region aso ...................... 9 2.6 sector protection control ....................... 9 3 data protection 10 3.1 device protection methods ..................... 10 3.2 command protection ......................... 11 3.3 secure silicon region (otp) .................... 12 3.4 sector protection methods ..................... 12 4 read operations 17 4.1 asynchronous read .......................... 17 4.2 page mode read ............................ 17 5 embedded operations 18 5.1 embedded algorithm controller (eac) ............. 18 5.2 program and erase summary ................... 19 5.3 command set .............................. 20 5.4 status monitoring ........................... 25 5.5 error types and clearing procedures .............. 26 5.6 embedded algorithm performance table ........... 27 6 software interface reference 28 6.1 command summary ......................... 28 6.2 device id and common flash interface (id-cfi) aso map ..................... 32 7 signal descriptions 38 7.1 address and data confguration . . . . . . . . . . . . . . . . . 38 7.2 input/output summary ........................ 38 7.3 versatile i/o feature .......................... 39 7.4 ready/busy# (ry/by#) ........................ 39 7.5 hardware reset ............................. 40 8 signal protocols 40 8.1 interface states ............................. 40 8.2 power-off with hardware data protection .......... 42 8.3 power conservation modes .................... 42 8.4 read ..................................... 43 9 electrical specifcations 45 9.1 absolute maximum ratings .................... 45 9.2 latchup characteristics ....................... 45 9.3 operating ranges ........................... 46 9.4 dc characteristics ........................... 48 9.5 capacitance characteristics .................... 50 10 timing specifcations 50 10.1 ac test conditions ........................... 50 10.2 power-on reset (por) and warm reset ........... 51 10.3 ac characteristics ........................... 54 11 physical interface 63 11.1 connection diagram ......................... 63 11.2 physical diagram C lae064 .................... 64 12 ordering information 65 *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 3 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 1 product overview the MYX29GL01GS11DPIV2 has a 16-bit (word) wide data bus and uses only word boundary addresses. all read accesses provide 16 bits of data on each bus transfer cycle. all writes take 16 bits of data from each bus transfer cycle. figure 1: block diagram 10 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet 1. product overview the gl-s family consists of 128-mbit to 1gbit, 3.0v core, versatile i/o, non-vola tile, flash memory devices. these devices have a 16-bit (word) wide data bus and use only word boundary addresses. all read accesses provide 16 bits of data on each bus transfer cycle. all writes take 16 bits of data from each bus transfer cycle. figure 1.1 block diagram : note: ** a max gl01gs = a25, a max gl512s = a24, a max gl256s = a23, a max gl128s = a22 the gl-s family combines the best features of execute in place (xip) and data storage flash memories. this MYX29GL01GS11DPIV2 has the fast random a ccess of xip flash along with the high density and fast program speed of data storage flash. read access to any random location takes 90 ns to 120 ns depending on device density and i/o power supply voltage. each random (initial) access reads an entire 32-byte aligned group of data called a page. other words within the same page may be read by cha nging only the low order 4 bits of word address. each access within the same page takes 15 ns to 30 ns. this is called page mode read. changing any of the higher word address bits will select a different page and begin a new initial access. all read accesses are asynchronous. inpu t/ou tpu t b u ffer s x-decoder y-decoder chip enab le o u tpu t enab le logic er as e volta ge gener ator pgm volt a ge gener a tor timer v cc detector s t a te control comma nd regis ter v cc v ss v io we# wp# ce# oe# s tb s tb dq15 ? dq0 s ector s witches ry/by# res et# d a t a l a tch y-ga ting cell m a trix address l a tch a m a x **?a0 the MYX29GL01GS11DPIV2 combines the best features of execute in place (xip) and data storage fash memories. this MYX29GL01GS11DPIV2 has the fast random access of xip fash along with the high density and fast program speed of data storage fash. read access to any random location takes 90 ns to 120 ns depending on device density and i/o power supply voltage. each random (initial) access reads an entire 32-byte aligned group of data called a page. other words within the same page may be read by changing only the low order 4 bits of word address. each access within the same page takes 15 ns to 30 ns. this is called page mode read. changing any of the higher word address bits will select a different page and begin a new initial access. all read accesses are asynchronous. note: a max gl01gs = a25 *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 4 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 2: address map type count addresses address within page 16 a3 - a0 address within write buffer 256 a7 - a0 page 4096 a15 - a4 write-buffer-line 256 a15 a8 sector 1024 (1 gb) 512 (512 mb) 256 (256 mb) 128 (128 mb) a max - a16 the device control logic is subdivided into two parallel operating sections, the host interface controller (hic) and the embedded algorithm controller (eac). hic monitors signal levels on the device inputs and drives outputs as needed to complete read and write data transfers with the host system. hic delivers data from the currently entered address map on read transfers; places write transfer address and data information into the eac command memory; notifes the eac of power transition, hardware reset, and write transfers. the eac looks in the command memory, after a write transfer, for legal command sequences and performs the related embedded algorithms. changing the non-volatile data in the memory array requires a complex sequence of operations that are called embedded algorithms (ea). the algorithms are managed entirely by the device internal eac. the main algorithms perform programming and erase of the main array data. the host system writes command codes to the fash device address space. the eac receives the commands, performs all the necessary steps to complete the command, and provides status information during the progress of an ea. the erased state of each memory bit is a logic 1. programming changes a logic 1 (high) to a logic 0 (low). only an erase operation is able to change a 0 to a 1. an erase operation must be performed on an entire 128-kbyte aligned and length group of data call a sector. programming is done via a 512-byte write buffer. it is possible to write from 1 to 256 words, anywhere within the write buffer before starting a programming operation. within the fash memory array, each 512-byte aligned group of 512 bytes is called a line. a programming operation transfers volatile data from the write buffer to a non-volatile memory array line. the operation is called write buffer programming. the write buffer is flled with 1s after reset or the completion of any operation using the write buffer. any locations not written to a 0 by a write to buffer command are by default still flled with 1s. any 1s in the write buffer do not affect data in the memory array during a programming operation. as each page of data that was loaded into the write buffer is transferred to a memory array line. sectors may be individually protected from program and erase operations by the advanced sector protection (asp) feature set. asp provides several, hardware and software controlled, volatile and non-volatile, methods to select which sectors are protected from program and erase operations. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 5 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* software interface 2 address space maps there are several separate address spaces that may appear within the address range of the fash memory device. one address space is visible (entered) at any given time. ? flash memory array: the main non-volatile memory array used for storage of data that may be randomly accessed by asynchronous read operations. ? id/cfi: a memory array used for factory programmed device characteristics information. this area contains the device identifcation (id) and common flash interface (cfi) information tables. ? secure silicon region (ssr): a one time programmable (otp) non-volatile memory array used for factory programmed permanent data, and customer programmable permanent data. ? lock register: an otp non-volatile word used to confgure the asp features and lock the ssr. ? persistent protection bits (ppb): a non-volatile fash memory array with one bit for each sector. when programmed, each bit protects the related sector from erasure and programming. ? ppb lock: a volatile register bit used to enable or disable programming and erasure of the ppb bits. ? password: an otp non-volatile array used to store a 64-bit password used to enable changing the state of the ppb lock bit when using password mode sector protection. ? dynamic protection bits (dyb): a volatile array with one bit for each sector. when set, each bit protects the related sector from erasure and programming. ? status register: a volatile register used to display embedded algorithm status. ? data polling status: a volatile register used as an alternate, legacy software compatible, way to display embedded algorithm status. the main flash memory array is the primary and default address space but, it may be overlaid by one other address space, at any one time. each alternate address space is called an address space overlay (aso). each aso replaces (overlays) the entire fash device address range. any address range not defned by a particular aso address map, is reserved for future use. all read accesses outside of an aso address map returns non-valid (undefned) data. the locations will display actively driven data but the meaning of whatever 1s or 0s appear are not defned. there are four device operating modes that determine what appears in the fash device address space at any given time: *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 6 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* ? read mode ? data polling mode ? status register (sr) mode ? address space overlay (aso) mode in read mode the entire flash memory array may be directly read by the host system memory controller. the memory device embedded algorithm controller (eac), puts the device in read mode during power-on, after a hardware reset, after a command reset, or after an embedded algorithm (ea) is suspended. read accesses and command writes are accepted in read mode. a subset of commands are accepted in read mode when an ea is suspended. while in any mode, the status register read command may be issued to cause the status register aso to appear at every word address in the device address space. in this status register aso mode, the device interface waits for a read access and, any write access is ignored. the next read access to the device accesses the content of the status register, exits the status register aso, and returns to the previous (calling) mode in which the status register read command was received. in ea mode the eac is performing an embedded algorithm, such as programming or erasing a non-volatile memory array. while in ea mode, none of the main flash memory array is readable because the entire fash device address space is replaced by the data polling status aso. data polling status will appear at every word location in the device address space. while in ea mode, only a program / erase suspend command or the status register read command will be accepted. all other commands are ignored. thus, no other aso may be entered from the ea mode. when an embedded algorithm is suspended, the data polling aso is visible until the device has suspended the ea. when the ea is suspended the data polling aso is exited and flash array data is available. the data polling aso is reentered when the suspended ea is resumed, until the ea is again suspended or fnished. when an embedded algorithm is completed, the data polling aso is exited and the device goes to the previous (calling) mode (from which the embedded algorithm was started). in aso mode, one of the remaining overlay address spaces is entered (overlaid on the main flash array address map). only one aso may be entered at any one time. commands to the device affect the currently entered aso. only certain commands are valid for each aso. these are listed in table 7: command defnitions (page 28 ) , in each aso related section of the table. the following asos have non-volatile data that may be programmed to change 1s to 0s: ? secure silicon region ? lock register ? persistent protection bits (ppb) ? password ? only the ppb aso has non-volatile data that may be erased to change 0s to 1s *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 7 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* when a program or erase command is issued while one of the non-volatile asos is entered, the ea operates on the aso. the aso is not readable while the ea is active. when the ea is completed the aso remains entered and is again readable. suspend and resume commands are ignored during an ea operating on any of these asos. 2 1 flash memory array the MYX29GL01GS11DPIV2 family has an uniform sector architecture with a sector size of 128 kb. table 3: MYX29GL01GS11DPIV2 sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 1024 sa00 0000000h-000ffffh sector starting address : : C sa1023 3ff0000h-3ffffffh sector ending address note: this table has been condensed to show sector related information for an entire device on a single page sectors and their address ranges that are not explicitly listed (such as sa001-sa510) have sectors starting and ending addresses that form the same pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xxx0000h-xxxffffh. 2 2 device id and cfi (id-cfi) aso there are two traditional methods for systems to identify the type of fash memory installed in the system. one has traditionally been called autoselect and is now referred to as device identifcation (id). the other method is called common flash interface (cfi). for id, a command is used to enable an address space overlay where up to 16 word locations can be read to get jedec manufacturer identifcation (id), device id, and some confguration and protection status information from the fash memory. the system can use the manufacturer and device ids to select the appropriate driver software to use with the fash device. cfi also uses a command to enable an address space overlay where an extendable table of standard information about how the fash memory is organized and operates can be read. with this method the driver software does not have to be written with the specifcs of each possible memory device in mind. instead the driver software is written in a more general way to handle many different devices but adjusts the driver behavior based on the information in the cfi table. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 8 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* traditionally these two address spaces have used separate commands and were separate overlays. however, the mapping of these two address spaces are non-overlapping and so can be combined in to a single address space and appear together in a single overlay. either of the traditional commands used to access (enter) the autoselect (id) or cfi overlay will cause the now combined id-cfi address map to appear. 2.2.1 device id the joint electron device engineering council (jedec) standard jep106t defnes the manufacturer id for a compliant memory. common industry usage defned a method and format for reading the manufacturer id and a device specifc id from a memory device. the manufacturer and device id information is primarily intended for programming equipment to automatically match a device with the corresponding programming algorithm. spansion has added additional felds within this 32-byte address space. 2.2.2 common flash memory interface the jedec common flash interface (cfi) specifcation (jesd68.01) defnes a standardized data structure that may be read from a fash memory device, which allows vendor-specifed software algorithms to be used for entire families of devices. the data structure contains information for system confguration such as various electrical and timing parameters, and special functions supported by the device. software support can then be device-independent, device id-independent, and forward-and-backward-compatible for entire flash device families. 2 3 status register aso the status register aso contains a single word of registered volatile status for embedded algorithms. when the status register read command is issued, the current status is captured (by the rising edge of we#) into the register and the aso is entered. the status register content appears on all word locations. the frst read access exits the status register aso (with the rising edge of ce# or oe#) and returns to the address space map in use when the status register read command was issued. write commands will not exit the status register aso state. 2 4 data polling status aso the data polling status aso contains a single word of volatile memory indicating the progress of an ea. the data polling status aso is entered immediately following the last write cycle of any command sequence that initiates an ea. commands that initiate an ea are: *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 9 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* ? word program ? program buffer to flash ? chip erase ? sector erase ? erase resume / program resume ? program resume enhanced method ? blank check ? lock register program ? password program ? ppb program ? all ppb erase the data polling status word appears at all word locations in the device address space. when an ea is completed the data polling status aso is exited and the device address space returns to the address map mode where the ea was started. 2 5 secure silicon region aso the secure silicon region (ssr) provides an extra fash memory area that can be programmed once and permanently protected from further changes i. e. it is a one time program (otp) area. the ssr is 1024 bytes in length. it consists of 512 bytes for factory locked secure silicon region and 512 bytes for customer locked secure silicon region. 2 6 sector protection control 2.6.1 lock register aso the lock register aso contains a single word of otp memory. when the aso is entered the lock register appears at all word locations in the device address space. however, it is recommended to read or program the lock register only at location 0 of the device address space for future compatibility. 2.6.2 persistent protection bits (ppb) aso the ppb aso contains one bit of a flash memory array for each sector in the device. when the ppb aso is entered, the ppb bit for a sector appears in the least signifcant bit (lsb) of each address in the sector. reading any address in a sector displays data where the lsb indicates the non-volatile protection status for that sector. however, it is recommended to read or program the ppb only at address 0 of the sector for future *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 10 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* compatibility. if the bit is 0 the sector is protected against programming and erase operations. if the bit is 1 the sector is not protected by the ppb. the sector may be protected by other features of asp. 2.6.3 ppb lock aso the ppb lock aso contains a single bit of volatile memory. the bit controls whether the bits in the ppb aso may be programmed or erased. if the bit is 0 the ppb aso is protected against programming and erase operations. if the bit is 1 the ppb aso is not protected. when the ppb lock aso is entered the ppb lock bit appears in the least signifcant bit (lsb) of each address in the device address space. however, it is recommended to read or program the ppb lock only at address 0 of the device for future compatibility. 2.6.4 password aso the password aso contains four words of otp memory. when the aso is entered the password appears starting at address 0 in the device address space. all locations above the forth word are undefned. 2.6.5 dynamic protection bits (dyb) aso the dyb aso contains one bit of a volatile memory array for each sector in the device. when the dyb aso is entered, the dyb bit for a sector appears in the least signifcant bit (lsb) of each address in the sector. reading any address in a sector displays data where the lsb indicates the non-volatile protection status for that sector. however, it is recommended to read, set, or clear the dyb only at address 0 of the sector for future compatibility. if the bit is 0 the sector is protected against programming and erase operations. if the bit is 1 the sector is not protected by the dyb. the sector may be protected by other features of asp. 3 data protection the device offers several features to prevent malicious or accidental modifcation of any sector via hardware means. 3 1 device protection methods 3.1.1 power-up write inhibit reset#, ce#, we#, and, oe# are ignored during power-on reset (por). during por, the device can not be selected, will not accept commands on the rising edge of we#, and does not drive outputs. the host interface controller (hic) and embedded algorithm controller (eac) are reset to their standby states, ready for reading array data, during por. ce# or oe# must go to v ih before the end of por (t vcs ). *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 11 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* at the end of por the device conditions are: ? all internal confguration information is loaded, ? the device is in read mode, ? the status register is at default value, ? all bits in the dyb aso are set to un-protect all sectors, ? the write buffer is loaded with all 1s, ? the eac is in the standby state. 3.1.2 low v cc write inhibit when v cc is less than v lko , the hic does not accept any write cycles and the eac resets. this protects data during v cc power-up and power-down. the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . 3 2 command protection embedded algorithms are initiated by writing command sequences into the eac command memory. the command memory array is not readable by the host system and has no aso. each host interface write is a command or part of a command sequence to the device. the eac examines the address and data in each write transfer to determine if the write is part of a legal command sequence. when a legal command sequence is complete the eac will initiate the appropriate ea. writing incorrect address or data values, or writing them in an improper sequence, will generally result in the eac returning to its standby state. however, such an improper command sequence may place the device in an unknown state, in which case the system must write the reset command, or possibly provide a hardware reset by driving the reset# signal low, to return the eac to its standby state, ready for random read. the address provided in each write may contain a bit pattern used to help identify the write as a command to the device. the upper portion of the address may also select the sector address on which the command operation is to be performed. the sector address (sa) includes amax through a16 fash address bits (system byte address signals amax through a17). a command bit pattern is located in a10 to a0 fash address bits (system byte address signals a11 through a1). the data in each write may be: a bit pattern used to help identify the write as a command, a code that identifes the command operation to be performed, or supply information needed to perform the operation. see table 7: command defnitions (page 28 ) for a listing of all commands accepted by the device. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 12 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 3 3 secure silicon region (otp) the secure silicon region (ssr) provides an extra fash memory area that can be programmed once and permanently protected from further changes i.e. it is a one time program (otp) area. the ssr is 1024 bytes in length. it consists of 512 bytes for factory locked secure silicon region and 512 bytes for customer locked secure silicon region. 3 4 sector protection methods 3.4.1 write protect signal if wp# = v il , the lowest or highest address sector is protected from program or erase operations independent of any other asp confguration. whether it is the lowest or highest sector depends on the device ordering option (model) selected. if wp# = v ih , the lowest or highest address sector is not protected by the wp# signal but it may be protected by other aspects of asp confguration. wp# has an internal pull-up; when unconnected, wp# is at v ih . 3.4.2 asp advanced sector protection (asp) is a set of independent hardware and software methods used to disable or enable programming or erase operations, individually, in any or all sectors. this section describes the various methods of protecting data stored in the memory array. an overview of these methods is shown in figure 2: advanced sector protection overview (page 13 ) . *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 13 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 2: advanced sector protection overview october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 19 data sheet 3.4 sector protection methods 3.4.1 write protect signal if wp# = v il , the lowest or highest address sector is prot ected from program or er ase operations independent of any other asp configuration. whether it is the lo west or highest sector depends on the device ordering option (model) selected. if wp# = v ih , the lowest or highest address sector is not protected by the wp# signal but it may be protected by other aspects of asp c onfiguration. wp# has an internal pull-up; when unconnected, wp# is at v ih . 3.4.2 asp advanced sector protection (asp) is a set of independe nt hardware and software methods used to disable or enable programming or erase operations, individually, in any or all sectors. this se ction describes the various methods of protecting data stored in the memory array. an overview of these methods is shown in figure 3.1 . figure 3.1 advanced sector protection overview every main flash array sector has a non-volatile (ppb) and a volatile (dyb) protection bit associated with it. when either bit is 0, the sector is prot ected from program an d erase operations. the ppb bits are protected from program and erase when the ppb lock bit is 0. there are two methods for managing the state of the ppb lock bit, persis tent protection and password protection. the persistent protection me thod sets the ppb lock to 1 during por or hardware reset so that the ppb bits are unprotected by a device reset. th ere is a command to clear the ppb lock bit to 0 to protect the ppb bits. p ass word method (dq2) per sistent method (dq1) lock regi ster (one time progr ammab le) ppb lock bit 1,2,3 64-bit p ass word (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory arr a y sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 4 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n per sistent protection bit (ppb) 5,6 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 7,8,9 7. 0 = sector protected, 1 = sector unprotected. 8 . protect effective only if corre sponding ppb is ?1? (unprotected). 9. vol atile bits : def aults to user choice upon power- up (s ee ordering options). 5. 0 = sector protected, 1 = sector unprotected. 6. ppb s progr ammed individua lly, bu t clea red collectively 1. bit i s vol a tile, and def aults to ?1? on reset (to ?0? if in p ass word mode). 2. progr amming to ?0? lock s all ppbs to their current sta te. 3 . once progr ammed to ?0?, requires hardw are reset to u nlock or a pplic ation of the pass word. 4. n = highe st address s ector. every main fash array sector has a non-volatile (ppb) and a volatile (dyb) protection bit associated with it. when either bit is 0, the sector is protected from program and erase operations. he ppb bits are protected from program and erase when the ppb lock bit is 0. there are two methods for managing the state of the ppb lock bit, persistent protection and password protection. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 14 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 3.4.3 sector protection states summary each sector can be in one of the following protection states: ? unlocked C the sector is unprotected and protection can be changed by a simple command. the protection state defaults to unprotected after a power cycle or hardware reset. ? dynamically locked C a sector is protected and protection can be changed by a simple command. the protection state is not saved across a power cycle or hardware reset. ? persistently locked C a sector is protected and protection can only be changed if the ppb lock bit is set to 1. the protection state is non-volatile and saved across a power cycle or hardware reset. changing the protection state requires programming or erase of the ppb bits. table 4: sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected - ppb and dyb are changeable 1 1 0 protected - ppb and dyb are changeable 1 0 1 protected - ppb and dyb are changeable 1 0 0 protected - ppb and dyb are changeable 0 1 1 unprotected - ppb not changeable, dyb is changeable 0 1 0 protected - ppb not changeable, dyb is changeable 0 0 1 protected - ppb not changeable, dyb is changeable 0 0 0 protected - ppb not changeable, dyb is changeable *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 15 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 3.4.4 lock register the lock register holds the non-volatile otp bits for controlling protection of the ssr, and determining the ppb lock bit management method (protection mode). table 5: lock register bit default value name 15-9 1 reserved 8 0 reserved 7 x reserved 6 1 ssr region 1 (customer) lock bit 5 1 reserved 4 1 reserved 3 1 reserved 2 1 password protection mode lock bit 1 1 persistent protection mode lock bit 0 0 ssr region 0 (factory) lock bit the secure silicon region (ssr) protection bits must be used with caution, as once locked, there is no procedure available for unlocking the protected portion of the secure silicon region and none of the bits in the protected secure silicon region memory space can be modifed in any way. once the secure silicon region area is protected, any further attempts to program in the area will fail with status indicating the area being programmed is protected. the region 0 indicator bit is located in the lock register at bit location 0 and region 1 in bit location 6. as shipped from the factory, all devices default to the persistent protection method, with all sectors unprotected, when power is applied. the device programmer or host system can then choose which sector protection method to use. programming either of the following two, one-time programmable, non-volatile bits, locks the part permanently in that mode: ? persistent protection mode lock bit (dq1) ? password protection mode lock bit (dq2) if both lock bits are selected to be programmed at the same time, the operation will abort. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled and no changes to the protection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 16 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* if the password mode is to be chosen, the password must be programmed prior to setting the corresponding lock register bit. setting the password protection mode lock bit is programmed, a power cycle, hardware reset, or ppb lock bit set command is required to set the ppb lock bit to 0 to protect the ppb array. the programming time of the lock register is the same as the typical word programming time. during a lock register programming ea, data polling status dq6 toggle bit i will toggle until the programming has completed. the system can also determine the status of the lock register programming by reading the status register. see section 5.4.1: status register (page 25 ) for information on these status bits. the user is not required to program dq2 or dq1, and dq6 or dq0 bits at the same time. this allows the user to lock the ssr before or after choosing the device protection scheme. when programming the lock bits, the reserved bits must be 1 (masked). 3.4.5 persistent protection mode the persistent protection method sets the ppb lock to 1 during por or hardware reset so that the ppb bits are unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. there is no command in the persistent protection method to set the ppb lock bit to 1 therefore the ppb lock bit will remain at 0 until the next power-off or hardware reset. 3.4.6 password protection mode 3.4.6.1 ppb password protection mode ppb password protection mode allows an even higher level of security than the persistent sector protection mode, by requiring a 64-bit password for setting the ppb lock. in addition to this password requirement, after power up and reset, the ppb lock is cleared to 0 to ensure protection at power-up. successful execution of the password unlock command by entering the entire password sets the ppb lock to 1, allowing for sector ppb modifcations. password protection notes: ? the password program command is only capable of programming 0s. ? the password is all 1s when shipped from the oem. it is located in its own memory space and is accessible through the use of the password program and password read commands. ? all 64-bit password combinations are valid as a password. ? once the password is programmed and verifed, the password mode locking bit must be set in order to prevent reading or modifcation of the password. ? the password mode lock bit, once programmed, prevents reading the 64-bit password on the data bus and further password programming. all further program and read commands to the password region are disabled (data is read as 1s) and these commands are ignored. there is no means to verify what the *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 17 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* password is after the password protection mode lock bit is programmed. password verifcation is only allowed before selecting the password protection mode. ? the password mode lock bit is not erasable. ? the exact password must be entered in order for the unlocking function to occur. ? the addresses can be loaded in any order but all 4 words are required for a successful match to occur. ? the sector addresses and word line addresses are compared while the password address/data are loaded. if the sector adddress dont match than the error will be reported at the end of that write cycle. the status register will return to the ready state with the program status bit set to 1, program status register bit set to 1, and write buffer abort status bit set to 1 indicating a failed programming operation. it is a failure to change the state of the ppb lock bit because it is still protected by the lack of a valid password. the data polling status will remain active, with dq7 set to the complement of the dq7 bit in the last word of the password unlock command, and dq6 toggling. ry/by# will remain low. ? the specifc address and data are compared after the program buffer to flash command has been given. if they dont match to the internal set value than the status register will return to the ready state with the program status bit set to 1 and program status register bit set to 1 indicating a failed programming operation. it is a failure to change the state of the ppb lock bit because it is still protected by the lack of a valid password. the data polling status will remain active, with dq7 set to the complement of the dq7 bit in the last word of the password unlock command, and dq6 toggling. ry/by# will remain low. ? the device requires approximately 100 s for setting the ppb lock after the valid 64-bit password is given to the device. ? the password unlock command cannot be accepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a password. the ea status checking methods may be used to determine when the eac is ready to accept a new password command. ? if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock. 4 read operations 4 1 asynchronous read each read access may be made to any location in the memory (random access). each random access is selftimed with the same latency from ce# or address to valid data (t acc or t ce ). *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 18 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 4 2 page mode read each random read accesses an entire 32-byte page in parallel. subsequent reads within the same page have faster read access speed. the page is selected by the higher address bits (a max -a4), while the specifc word of that page is selected by the least signifcant address bits a3-a0. the higher address bits are kept constant and only a3-a0 changed to select a different word in the same page. this is an asynchronous access with data appearing on dq15-dq0 when ce# remains low, oe# remains low, and the asynchronous page access time (t pacc ) is satisfed. if ce# goes high and returns low for a subsequent access, a random read access is performed and time is required (t acc or tce). 5 embedded operations 5 1 embedded algorithm controller (eac) the eac takes commands from the host system for programming and erasing the fash memory array and performs all the complex operations needed to change the non-volatile memory state. this frees the host system from any need to manage the program and erase processes. there are four eac operation categories: ? standby (read mode) ? address space switching ? embedded algorithms (ea) ? advanced sector protection (asp) management 5.1.1 eac standby in the standby mode current consumption is greatly reduced. the eac enters its standby mode when no command is being processed and no embedded algorithm is in progress. if the device is deselected (ce# = high) during an embedded algorithm, the device still draws active current until the operation is completed (i cc3 ). i cc4 in section 9.4: dc characteristics (page 48 ) represents the standby current specifcation when both the host interface and eac are in their standby state. 5.1.2 address space switching writing specifc address and data sequences (command sequences) switch the memory device address space from the main fash array to one of the address space overlays (aso). *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 19 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* embedded algorithms operate on the information visible in the currently active (entered) aso. the system continues to have access to the aso until the system issues an aso exit command, performs a hardware reset, or until power is removed from the device. an aso exit command switches from an aso back to the main fash array address space. the commands accepted when a particular aso is entered are listed between the aso enter and exit commands in the command defnitions table. see table 7: command defnitions (page 28 ) for address and data requirements for all command sequences. 5.1.3 embedded algorithms (ea) changing the non-volatile data in the memory array requires a complex sequence of operations that are called embedded algorithms (ea). the algorithms are managed entirely by the device internal embedded algorithm controller (eac). the main algorithms perform programming and erasing of the main array data and the asos. the host system writes command codes to the fash device address space. the eac receives the commands, performs all the necessary steps to complete the command, and provides status information during the progress of an ea. 5 2 program and erase summary flash data bits are erased in parallel in a large group called a sector. the erase operation places each data bit in the sector in the logical 1 state (high). flash data bits may be individually programmed from the erased 1 state to the programmed logical 0 (low) state. a data bit of 0 cannot be programmed back to a 1. a succeeding read shows that the data is still 0. only erase operations can convert a 0 to a 1. programming the same word location more than once with different 0 bits will result in the logical and of the previous data and the new data being programmed. 5.2.1 program granularity the MYX29GL01GS11DPIV2 supports two methods of programming, word or write buffer programming. each page can be programmed by either method. pages programmed by different methods may be mixed within a line for the industrial temperature version (-40c to +85c). 5.2.2 incremental programming the same word location may be programmed more than once, by either the word or write buffer programming methods, to incrementally change 1s to 0s. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 20 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 5 3 command set 5.3.1 program methods 5.3.1.1 word programming word programming is used to program a single word anywhere in the main flash memory array. the word programming command is a four-write-cycle sequence. the program command sequence is initiated by writing two unlock write cycles, followed by the program set up command. the program address and data are written next, which in turn initiate the embedded word program algorithm. the system is not required to provide further controls or timing. the device automatically generates the program pulses and verifes the programmed cell margin internally. when the embedded word program algorithm is complete, the eac then returns to its standby mode. 5.3.1.2 write buffer programming a write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (line). thus, a full write buffer programming operation must be aligned on a line boundary. programming operations of less than a full 512 bytes may start on any word boundary but may not cross a line boundary. at the start of a write buffer programming operation all bit locations in the buffer are all 1s (ffffh words) thus any locations not loaded will retain the existing data. write buffer programming allows up to 512 bytes to be programmed in one operation. it is possible to program from 1 bit up to 512 bytes in each write buffer programming operation. it is recommended that a multiple of pages be written and each page written only once. for the very best performance, programming should be done in full lines of 512 bytes aligned on 512-byte boundaries. write buffer programming is supported only in the main fash array or the ssr aso. the write buffer programming sequence can be stopped by the following: hardware reset or power cycle. however, using either of these methods may leave the area being programmed in an intermediate state with invalid or unstable data values. in this case the same area will need to be reprogrammed with the same data or erased to ensure data values are properly programmed or erased. 5.3.2 program suspend / program resume commands the program suspend command allows the system to interrupt an embedded programming operation so that data can read from any non-suspended line. when the program suspend command is written during a programming process, the device halts the programming operation within t psl (program suspend latency) and updates the status bits. addresses are dont-cares when writing the program suspend command. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 21 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* there are two commands available for program suspend. the legacy combined erase / program suspend command (b0h command code) and the separate program suspend command (51h command code). there are also two commands for program resume. the legacy combined erase / program resume command (30h command code) and the separate program resume command (50h command code). it is recommended to use the separate program suspend and resume commands for programming and use the legacy combined command only for erase suspend and resume. 5.3.3 blank check the blank check command will confrm if the selected main fash array sector is erased. the blank check command does not allow for reads to the array during the blank check. reads to the array while this command is executing will return unknown data. 5.3.4 erase methods 5.3.4.1 chip erase the chip erase function erases the entire main flash memory array. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifes the entire memory for an all 0 data pattern prior to electrical erase. after a successful chip erase, all locations within the device contain ffffh. the system is not required to provide any controls or timings during these operations. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. when we# goes high, at the end of the 6th cycle, the ry/by# goes low. 5.3.4.2 sector erase the sector erase function erases one sector in the memory array. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifes the entire sector for an all 0 data pattern prior to electrical erase. after a successful sector erase, all locations within the erased sector contain ffffh. the system is not required to provide any controls or timings during these operations. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. when we# goes high, at the end of the 6th cycle, the ry/by# goes low. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 22 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 5.3.5 erase suspend / erase resume the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main fash array. this command is valid only during sector erase or program operation. the erase suspend command is ignored if written during the chip erase operation. 5.3.6 aso entry and exit 5.3.6.1 id-cfi aso the system can access the id-cfi aso by issuing the id-cfi entry command sequence during read mode. this entry command uses the sector address (sa) in the command to determine which sector will be overlaid and which sectors protection state is reported in word location 2h. see table 8: id (autoselect) address map (page 33 ) . 5.3.6.2 status register aso the status register aso contains a single word of registered volatile status for embedded algorithms. when the status register read command is issued, the current status is captured (by the rising edge of we#) into the register and the aso is entered. the status register content appears on all word locations. the frst read access exits the status register aso (with the rising edge of ce# or oe#) and returns to the address space map in use when the status register read command was issued. write commands will not exit the status register aso state. 5.3.6.3 secure silicon region aso the system can access the secure silicon region by issuing the secure silicon region entry command sequence during read mode. this entry command uses the sector address (sa) in the command to determine which sector will be overlaid. the secure silicon region aso allows the following activities: ? read secure silicon regions. ? programming the customer secure silicon region is allowed using the word or write buffer programming commands. ? aso exit using legacy secure silicon exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 23 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 5.3.6.4 lock register aso the system can access the lock register by issuing the lock register entry command sequence during read mode. this entry command does not use a sector address from the entry command. the lock register appears at word location 0 in the device address space. all other locations in the device address space are undefned. the lock register aso allows the following activities: ? read lock register, using device address location 0. ? program the customer lock register using a modifed word programming command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.5 password aso the system can access the password aso by issuing the password entry command sequence during read mode. this entry command does not use a sector address from the entry command. the password appears at word locations 0 to 3 in the device address space. all other locations in the device address space are undefned. the password aso allows the following activities: ? read password, using device address location 0 to 3. ? program the password using a modifed word programming command. ? unlock the ppb lock bit with the password unlock command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.6 ppb aso the system can access the ppb aso by issuing the ppb entry command sequence during read mode. this entry command does not use a sector address from the entry command. the ppb bit for a sector appears in bit 0 of all word locations in the sector. the ppb aso allows the following activities: ? read ppb protection status of a sector in bit 0 of any word in the sector. ? program the ppb bit using a modifed word programming command. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 24 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* ? erase all ppb bits with the ppb erase command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.7 ppb lock aso the system can access the ppb lock aso by issuing the ppb lock entry command sequence during read mode. this entry command does not use a sector address from the entry command. the global ppb lock bit appears in bit 0 of all word locations in the device. the ppb lock aso allows the following activities: ? read ppb lock protection status in bit 0 of any word in the device address space. ? set the ppb lock bit using a modifed word programming command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.8 dyb aso the system can access the dyb aso by issuing the dyb entry command sequence during read mode. this entry command does not use a sector address from the entry command. the dyb bit for a sector appears in bit 0 of all word locations in the sector. the dyb aso allows the following activities: ? read dyb protection status of a sector in bit 0 of any word in the sector. ? set the dyb bit using a modifed word programming command. ? clear the dyb bit using a modifed word programming command. ? aso exit using legacy command set exit command for backward software compatibility. ? aso exit using the common exit command for all aso - alternative for a consistent exit method. 5.3.6.9 software (command) reset / aso exit software reset is part of the command set (aee table 7: command defnitions (page 28 ) ) that also returns the eac to standby state and must be used for the following conditions: ? exit id/cfi mode ? clear timeout bit (dq5) for data polling when timeout occurs *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 25 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* software reset does not affect ea mode. reset commands are ignored once programming or erasure has begun, until the operation is complete. software reset does not affect outputs; it serves primarily to return to read mode from an aso mode or from a failed program or erase operation. software reset may cause a return to read mode from undefned states that might result from invalid command sequences. however, a hardware reset may be required to return to normal operation from some undefned states. there is no software reset latency requirement. the reset command is executed during the t wph period. 5 4 status monitoring there are three methods for monitoring ea status. previous generations of the MYX29GL01GS11DPIV2 used the methods called data polling and ready/busy# (ry/by#) signal. these methods are still supported by the MYX29GL01GS11DPIV2. one additional method is reading the status register. 5.4.1 status register the status of program and erase operations is provided by a single 16-bit status register. the status is receiver by writing the status register read command followed by a read access. when the status register read command is issued, the current status is captured (by the rising edge of we#) into the register and the aso is entered. the contents of the status register is aliased (overlaid) on the full memory address space. any valid read (ce# and oe# low) access while in the status register aso will exit the aso (with the rising edge of ce# or oe# for t ceph /t oeph time) and return to the address space map in use when the status register read command was issued. the status register contains bits related to the results - success or failure - of the most recently completed embedded algorithms (ea): ? erase status (bit 5), ? program status (bit 4), ? write buffer abort (bit 3), ? sector locked status (bit 1), ? rfu (bit 0). and, bits related to the current state of any in process ea: ? device busy (bit 7), ? erase suspended (bit 6), ? program suspended (bit 2), the current state bits indicate whether an ea is in process, suspended, or completed. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 26 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 5.4.2 data polling status during an active embedded algorithm the eac switches to the data polling aso to display ea status to any read access. a single word of status information is aliased in all locations of the device address space. in the status word there are several bits to determine the status of an ea. these are referred to as dq bits as they appear on the data bus during a read access while an ea is in progress. dq bits 15 to 8, dq4, and dq0 are reserved and provide undefned data. status monitoring software must mask the reserved bits and treat them as dont care. 5 5 error types and clearing procedures there are three types of errors reported by the embedded operation status methods. depending on the error type, the status reported and procedure for clearing the error status is different. following is the clearing of error status: ? if an aso was entered before the error the device remains entered in the aso awaiting aso read or a command write. ? if an erase was suspended before the error the device returns to the erase suspended state awaiting fash array read or a command write. ? otherwise, the device will be in standby state awaiting fash array read or a command write. 5.5.1 embedded operation error if an error occurs during an embedded operation (program, erase, blank check, or password unlock) the device (eac) remains busy. the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the status register shows ready with valid status bits. the device remains busy until the error status is detected by the host system status monitoring and the error status is cleared. 5.5.2 protection error if an embedded algorithm attempts to change data within a protected area (program, or erase of a protected sector or otp area) the device (eac) goes busy for a period of 20 to 100 s then returns to normal operation. during the busy period the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the status register shows not ready with invalid status bits (sr[7] = 0). 5.5.3 write buffer abort if an error occurs during a write to buffer command the device (eac) remains busy. the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the status register shows ready with valid status bits. the device remains busy until the error status is detected by the host system status monitoring and the error status is cleared. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 27 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 5 6 embedded algorithm performance table table 6: embedded algorithm characteristics (-40c to +85c) parameter typ 2 max 3 unit comments sector erase time 128 kbyte 275 1100 ms includes pre-programming prior to erasure 5 single word programming time 1 125 400 s buffer programming time 2-byte 1 125 750 s 32-byte 1 160 750 64-byte 1 175 750 128-byte 1 198 750 256-byte 1 239 750 512-byte 340 750 effective write buffer program operation per word 512-byte 1.33 s sector programming time 128 kb (full buffer programming) 108 192 ms note 6 erase suspend/erase resume (t esl ) 40 s program suspend/program resume (t psl ) 40 s erase resume to next erase suspend (t ers ) 100 s minimum of 60 ns but typical periods are needed for erase to progress to completion. program resume to next program suspend (t prs ) 100 s minimum of 60 ns but typical periods are needed for program to progress to completion. blank check 6.2 8.5 ms nop (number of program-operations, per line) 256 notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25c, 3.0v v cc , 10,000 cycle, and a random data pattern. 3. under worst case conditions of 90c, v cc = 2.70v, 100,000 cycles, and a random data pattern. 4. effective write buffer specifcation is based upon a 512-byte write buffer operation. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 0000h before sector and chip erasure. 6. system-level overhead is the time required to execute the bus-cycle sequence for the program command. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 28 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 6 software interface reference 6 1 command summary table 7: command defnitions command sequence 1 cycles bus cycles 2-5 first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data read 6 1 ra rd reset/aso exit 7,16 1 xxx f0 status register read 2 555 70 xxx rd status register clear 1 555 71 word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confrm) 1 sa 29 write-to-buffer-abort reset 11 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend legacy method 9 1 xxx b0 erase suspend enhanced method erase resume/program resume legacy method 10 1 xxx 30 erase resume enhanced method program suspend enhanced method 1 xxx 51 program resume enhanced method 1 xxx 50 blank check 1 (sa) 555 33 *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 29 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 7: command defnitions (continued) command sequence 1 cycles bus cycles 2-5 first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data id-cfi (autoselect) aso id (autoselect) entry 3 555 aa 2aa 55 (sa) 555 90 cfi enter (note 8) 1 (sa) 55 98 id-cfi read 1 ra rd reset/aso exit (notes 7, 16) 1 xxx f0 secure silicon region command defnitions secure silicon region (ssr) aso ssr entry 3 555 aa 2aa 55 (sa) 555 88 read 6 1 ra rd word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confrm) 1 sa 29 write-to-buffer-abort reset 11 3 555 aa 2aa 55 555 f0 ssr exit 11 4 555 aa 2aa 55 555 90 xx 0 reset/aso exit 7, 16 1 xxx f0 lock register command set defnitions lock register aso lock register entry 3 555 aa 2aa 55 555 40 program 15 2 xxx a0 xxx pd read 15 1 0 rd command set exit 12, 16 2 xxx 90 xxx 0 reset/aso exit 7, 16 1 xxx f0 *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 30 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 7: command defnitions (continued) command sequence 1 cycles bus cycles 2-5 first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data password protection command set defnitions password aso password aso entry 3 555 aa 2aa 55 555 60 program 14 2 xxx a0 pwax pwdx read 13 4 0 pwd0 1 pwd1 2 pwd2 3 pwd 3 unlock 7 0 25 0 3 0 pwd0 1 pwd 1 2 pwd2 3 pwd 3 0 29 command set exit 12, 16 2 xxx 90 xxx 0 reset/aso exit 7, 16 1 xxx f0 non-volatile sector protection command set defnitions ppb (non-volatile sector protection) ppb entry 3 555 aa 2aa 55 555 c0 ppb program 17 2 xxx a0 sa 0 all ppb erase 17 2 xxx 80 0 30 ppb read 17 1 sa rd (0) command set exit 12, 16 2 xxx 90 xxx 0 reset/aso exit 7, 16 1 xxx f0 global non-volatile sector protection freeze command set defnitions ppb lock bit ppb lock entry 3 555 aa 2aa 55 555 50 ppb lock bit cleared 2 xxx a0 xxx 0 ppb lock status read 17 1 xxx rd (0) command set exit 12, 16 2 xxx 90 xxx 0 reset/aso exit 7, 16 1 xxx f0 volatile sector protection command set defnitions dyb (volatile sector protection) aso dyb aso entry 3 555 aa 2aa 55 555 e0 dyb set 17 2 xxx a0 sa 0 dyb clear 17 2 xxx a0 sa 1 dyb status read 17 1 sa rd (0) command set exit 12, 16 2 xxx 90 xxx 0 reset/aso exit 16 1 xxx f0 *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 31 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 7: command defnitions (continued) legend: ? x = don't care. ? ra = address of the memory to be read. ? rd = data read from location ra during read operation. ? pa = address of the memory location to be programmed. ? pd = data to be programmed at location pa. ? sa = address of the sector selected. address bits a max -a16 uniquely select any sector. ? wbl = write buffer location. the address must be within the same line. ? wc = word count is the number of write buffer locations to load minus 1. ? pwax = password address for word0 = 00h, word1 = 01h, word2 = 02h, and word3 = 03h. ? pwdx = password data word0, word1, word2, and word3. notes: 1. see table 15: interface states (page 41 ) for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle during read, id/cfi read (manufacturing id / device id), indicator bits, secure silicon region read, ssr lock read, and 2nd cycle of status register read . 4. data bits dq15-dq8 are dont care in command sequences, except for rd, pd, wc and pwd. 5. address bits a max -a11 are dont cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the id-cfi (autoselect) mode, or if dq5 goes high (while the device is providing status data). 8. command is valid when device is ready to read array data or when device is in id-cfi (autoselect) mode. 9. the system can read and program/program suspend in non-erasing sectors, or enter the id-cfi aso, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 11. issue this command sequence to return to read mode after detecting device is in a write-to-buffer-abort state. important: the full command sequence is required if resetting out of abort. 12. the exit command returns the device to reading the array. 13. the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 32 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 14. for pwdx, only one portion of the password can be programmed per each a0 command. portions of the password must be programmed in sequential order (pwd0 - pwd3). 15. all lock register bits are one-time programmable. the program state = 0 and the erase state = 1. also, both the persistent protection mode lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation aborts and returns the device to read mode. lock register bits that are reserved for future use are undefned and may be 0s or 1s. 16. if any of the entry commands was issued, an exit command must be issued to reset the device into read mode. 17. protected state = 00h, unprotected state = 01h. the sector address for dyb set, dyb clear, or ppb program command may be any location within the sector - the lower order bits of the sector address are dont care. 6 2 device id and common flash interface (id-cfi) aso map the device id portion of the aso (word locations 0h to 0fh) provides manufacturer id, device id, sector protection state, and basic feature set information for the device. id-cfi location 02h displays sector protection status for the sector selected by the sector address (sa) used in the id-cfi enter command. to read the protection status of more than one sector it is necessary to exit the id aso and enter the id aso using the new sa. the access time to read location 02h is always t acc and a read of this location requires ce# to go high before the read and return low to initiate the read (asynchronous read access). page mode read between location 02h and other id locations is not supported. page mode read between id locations other than 02h is supported. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 33 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 8: id (autoselect) address map description address read data manufacture id (sa) + 0000h 0001h device id (sa) + 0001h 227eh protection verifcation (sa) + 0002h sector protection state (1= sector protected, 0= sector unprotected). this protection state is shown only for the sa selected when entering id-cfi aso. reading other sa provides undefned data. to read a different sa protection state aso exit command must be used and then enter id-cfi aso again with the new sa. indicator bits (sa) + 0003h dq15-dq08 = 1 (reserved) dq7 - factory locked secure silicon region 1 = locked, 0 = not locked dq6 - customer locked secure silicon region 1 = locked 0 = not locked dq5 = 1 (reserved) dq4 - wp# protects 0 = lowest address sector 1 = highest address sector dq3 - dq0 = 1 (reserved) rfu (sa) + 0004h reserved (sa) + 0005h reserved (sa) + 0006h reserved (sa) + 0007h reserved (sa) + 0008h reserved (sa) + 0009h reserved (sa) + 000ah reserved (sa) + 000bh reserved lower software bits (sa) + 000ch bit 0 - status register support 1 = status register supported 0 = status register not supported bit 1 - dq polling support 1 = dq bits polling supported 0 = dq bits polling not supported bit 3-2 - command set support 11 = reserved 10 = reserved 01 = reduced command set 00 = classic command set bits 4-15 - reserved = 0 upper software bits (sa) + 000dh reserved device id (sa) + 000eh 2228h = 1 gb 2223h = 512 mb 2222h = 256 mb 2221h = 128 mb device id (sa) + 000fh 2201h *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 34 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 9: cfi query identifcation string word address data description (sa) + 0010h (sa) + 0011h (sa) + 0012h 0051h 0052h 0059h query unique ascii string qry (sa) + 0013h (sa) + 0014h 0002h 0000h primary oem command set (sa) + 0015h (sa) + 0016h 0040h 0000h address for primary extended table (sa) + 0017h (sa) + 0018h 0000h 0000h alternate oem command set (00h = none exists) (sa) + 0019h (sa) + 001ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 10: cfi system interface string word address data description (sa) + 001bh 0027h v cc min. (erase/program) (d7-d4: volts, d3-d0: 100 mv) (sa) + 001ch 0036h v cc max. (erase/program) (d7-d4: volts, d3-d0: 100 mv) (sa) + 001dh 0000h v pp min. voltage (00h = no v pp pin present) (sa) + 001eh 0000h v pp max. voltage (00h = no v pp pin present) (sa) + 001fh 0008h typical timeout per single word write 2n s (sa) + 0020h 0009h typical timeout for max multi-byte program, 2n s (00h = not supported) (sa) + 0021h 0008h typical timeout per individual block erase 2n ms (sa) + 0022h 0012h (1 gb) 0011h (512 mb) 0010h (256 mb) 000fh (128 mb) typical timeout for full chip erase 2n ms (00h = not supported) (sa) + 0023h 0001h max. timeout for single word write 2n times typical (sa) + 0024h 0002h max. timeout for buffer write 2n times typical (sa) + 0025h 0003h max. timeout per individual block erase 2n times typical (sa) + 0026h 0003h max. timeout for full chip erase 2n times typical (00h = not supported) *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 35 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 11: cfi device geometry defnition word address data description (sa) + 0027h 001bh (1 gb) 001ah (512 mb) 0019h (256 mb) 0018h (128 mb) device size = 2 n byte; (sa) + 0028h 0001h flash device interface description 0 = x8-only, 1 = x16-only, 2 = x8/x16 capable (sa) + 0029h 0000h (sa) + 002ah 0009h max. number of byte in multi-byte write = 2 n (00 = not supported) (sa) + 002bh 0000h (sa) + 002ch 0001h number of erase block regions within device; 1 = uniform device, 2 = boot device (sa) + 002dh 00xxh erase block region 1 information (refer to jedec jesd68-01 or jep137 specifcations) 00ffh, 0003h, 0000h, 0002h =1 gb 00ffh, 0001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 0000h, 0002h = 128 mb (sa) + 002eh 000xh (sa) + 002fh 0000h (sa) + 0030h 000xh (sa) + 0031h 0000h erase block region 2 information (refer to cfi publication 100) (sa) + 0032h 0000h (sa) + 0033h 0000h (sa) + 0034h 0000h (sa) + 0035h 0000h erase block region 3 information (refer to cfi publication 100) (sa) + 0036h 0000h (sa) + 0037h 0000h (sa) + 0038h 0000h (sa) + 0039h 0000h erase block region 4 information (refer to cfi publication 100) (sa) + 003ah 0000h (sa) + 003bh 0000h (sa) + 003ch 0000h (sa) + 003dh ffffh reserved (sa) + 003eh ffffh reserved (sa) + 003fh ffffh reserved *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 36 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 12: cfi primary vendor-specifc extended query word address data description (sa) + 0040h 0050h query-unique ascii string pri (sa) + 0041h 0052h (sa) + 0042h 0049h (sa) + 0043h 0031h major version number, ascii (sa) + 0044h 0035h minor version number, ascii (sa) + 0045h 001ch address sensitive unlock (bits 1-0) 00b = required 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.13 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 0110b = 0.09 m floating gate 0111b = 0.065 m mirrorbit eclipse 1000b = 0.065 m mirrorbit 1001b = 0.045 m mirrorbit (sa) + 0046h 0002h erase suspend 0 = not supported 1 = read only 2 = read and write (sa) + 0047h 0001h sector protect 00 = not supported x = number of sectors in smallest group (sa) + 0048h 0000h temporary sector unprotect 00 = not supported 01 = supported (sa) + 0049h 0008h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method (sa) + 004ah 0000h simultaneous operation 00 = not supported x = number of banks (sa) + 004bh 0000h burst mode type 00 = not supported 01 = supported *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 37 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* word address data description (sa) + 004ch 0003h page mode type 00 = not supported 01 = 4 word page 02 = 8 word page 03=16 word page (sa) + 004dh 0000h acc (acceleration) supply minimum 00 = not supported d7-d4: volt d3-d0: 100 mv (sa) + 004eh 0000h acc (acceleration) supply maximum 00 = not supported d7-d4: volt d3-d0: 100 mv (sa) + 004fh 0004h (bottom) 0005h (top) wp# protection 00h = flash device without wp protect (no boot) 01h = eight 8 kb sectors at top and bottom with wp (dual boot) 02h = bottom boot device with wp protect (bottom boot) 03h = top boot device with wp protect (top boot) 04h = uniform, bottom wp protect (uniform bottom boot) 05h = uniform, top wp protect (uniform top boot) 06h = wp protect for all sectors 07h = uniform, top and bottom wp protect (sa) + 0050h 0001h program suspend 00 = not supported 01 = supported (sa) +0051h 0000h unlock bypass 00 = not supported 01 = supported (sa) + 0052h 0009h secured silicon sector (customer otp area) size 2n (bytes) (sa) + 0053h 008fh software features bit 0: status register polling (1 = supported, 0 = not supported) bit 1: dq polling (1 = supported, 0 = not supported) bit 2: new program suspend/resume commands (1 = supported, 0 = not supported) bit 3: word programming (1 = supported, 0 = not supported) bit 4: bit-feld programming (1 = supported, 0 = not supported) bit 5: autodetect programming (1 = supported, 0 = not supported) bit 6: rfu bit 7: multiple writes per line (1 = supported, 0 = not supported) table 12: cfi primary vendor-specifc extended query (continued) *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 38 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* word address data description (sa) + 0054h 0005h page size = 2 n bytes (sa) + 0055h 0006h erase suspend timeout maximum < 2 n (s) (sa) + 0056h 0006h program suspend timeout maximum < 2 n (s) (sa) + 0057h to (sa) + 0077h ffffh reserved (sa) + 0078h 0006h embedded hardware reset timeout maximum < 2 n (s) reset with reset pin (sa) + 0079h 0009h non-embedded hardware reset timeout maximum < 2n ( s) power on reset 7 signal descriptions 7 1 address and data confguration address and data are connected in parallel (adp) via separate signal inputs and i/os. 7 2 input/output summary table 13: i/o summary symbol type description reset# input hardware reset. at v il , causes the device to reset control logic to its standby state, ready for reading array data. ce# input chip enable. at v il , selects the device for data transfer with the host memory controller. oe# input output enable. at v il , causes outputs to be actively driven. at v ih , causes outputs to be high impedance (high-z). we# input write enable. at v il , indicates data transfer from host to device. at v ih , indicates data transfer is from device to host. a max -a0 input address input. a25-a0 dq15-dq0 input/output data inputs and outputs. wp# input write protect. at v il , disables program and erase functions in the lowest or highest address 64-kword (128-kb) sector of the device. at v ih , the sector is not protected. wp# has an internal pull up; when unconnected wp# is at v ih . table 12: cfi primary vendor-specifc extended query (continued) *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 39 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* symbol type description ry/by# output - open drain ready/busy. indicates whether an embedded algorithm is in progress or complete. at v il , the device is actively engaged in an embedded algorithm such as erasing or programming. at high-z, the device is ready for read or a new command write - requires external pull-up resistor to detect the high-z state. multiple devices may have their ry/by# outputs tied together to detect when all devices are ready. v cc power supply core power supply v io power supply versatile io power supply. v ss power supply power supplies ground nc no connect not connected internally. the pin/ball location may be used in printed circuit board (pcb) as part of a routing channel. rfu no connect reserved for future use. not currently connected internally but the pin/ball location should be left unconnected and unused by pcb routing channel for future compatibility. the pin/ball may be used by a signal in the future. dnu reserved do not use. reserved for use by the ocm. the pin/all is connected internally. the input has an internal pull down resistance to v ss . the pin/ball can be left open or tied to v ss on the pcb. 7 3 versatile i/o feature the maximum output voltage level driven by, and input levels acceptable to, the device are determined by the v io power supply. this supply allows the device to drive and receive signals to and from other devices on the same bus having interface signal levels different from the device core voltage. 7 4 ready/busy# (ry/by#) ry/by# is a dedicated, open drain output pin that indicates whether an embedded algorithm, power-on reset (por), or hardware reset is in progress or complete. the ry/by# status is valid after the rising edge of the fnal we# pulse in a command sequence, when v cc is above v cc minimum during por, or after the falling edge of reset#. since ry/by# is an open drain output, several ry/by# pins can be tied together in parallel with a pull up resistor to v io . if the output is low (busy), the device is actively erasing, programming, or resetting. (this includes programming in the erase suspend mode). if the output is high (ready), the device is ready to read data (including during the erase suspend mode), or is in the standby mode. if an embedded algorithm has failed (program / erase failure as result of max pulses or sector is locked), ry/ by# will stay low (busy) until status register bits 4 and 5 are cleared and the reset command is issued. this includes erase or programming on a locked sector. table 13: i/o summary (continued) *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 40 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 7 5 hardware reset the reset# input provides a hardware method of resetting the device to standby state. when reset# is driven low for at least a period of t rp , the device immediately: ? terminates any operation in progress, ? exits any aso, ? tristates all outputs, ? resets the status register, ? resets the eac to standby state. ? ce# is ignored for the duration of the reset operation (t rph ). ? to meet the reset current specifcation (i cc5 ) ce# must be held high. to ensure data integrity any operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. 8 signal protocols the following sections describe the host system interface signal behavior and timing for the MYX29GL01GS11DPIV2. 8 1 interface states table 15 describes the required value of each interface signal for each interface state. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 41 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 15: interface states interface state v cc v io reset# ce# oe# we# a max -a0 dq15-dq0 power-off with hardware data protection < v lko v cc x x x x x high-z power-on (cold) reset v cc min v io min; v cc x x x x x high-z hardware (warm) reset v cc min v io min; v cc l x x x x high-z interface standby v cc min v io min; v cc h h x x x high-z automatic sleep 1, 3 v cc min v io min; v cc h l x x valid output available read with output disable 2 v cc min v io min; v cc h l h h valid high-z random read v cc min v io min h l l h valid output valid page read v cc min v io min; v cc h l l h a max -a4 valid a3-a0 modifed output valid write v cc min v io min; v cc h l h l valid input valid legend: 1. l = v il 2. h = v ih 3. x = either v il or v ih 4. l/h = rising edge 5. h/l = falling edge 6. valid = all bus signals have stable l or h level 7. modifed = valid state different from a previous valid state 8. available = read data is internally stored with output driver controlled by oe# notes: 1. we# and oe# can not be at v il at the same time. 2. read with output disable is a read initiated with oe# high. 3. automatic sleep is a read/write operation where data has been driven on the bus for an extended period, without ce# going high and the device internal logic has gone into standby mode to conserve power. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 42 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 8 2 power-off with hardware data protection the memory is considered to be powered off when the core power supply (v cc ) drops below the lock-out voltage (v lko ). when v cc is below v lko , the entire memory array is protected against a program or erase operation. this ensures that no spurious alteration of the memory content can occur during power transition. during a power supply transition down to power-off, v io should remain less than or equal to v cc . if v cc goes below v rst (min) then returns above v rst (min) to v cc minimum, the power-on reset interface state is entered and the eac starts the cold reset embedded algorithm. 8 3 power conservation modes 8.3.1 interface standby standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (ce# = high). all inputs are ignored in this state and all outputs except ry/by# are high impedance. ry/by# is a direct output of the eac, not controlled by the host interface. 8.3.2 automatic sleep the automatic sleep mode reduces device interface energy consumption to the sleep level (i cc6 ) following the completion of a random read access time. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. while in sleep mode, output data is latched and always available to the system. output of the data depends on the level of the oe# signal but, the automatic sleep mode current is independent of the oe# signal level. standard address access timings (t acc or t pacc ) provide new data when addresses are changed. i cc6 in section 9.4: dc characteristics (page 48 ) represents the automatic sleep mode current specifcation. automatic sleep helps reduce current consumption especially when the host system clock is slowed for power reduction. during slow system clock periods, read and write cycles may extend many times their length versus when the system is operating at high speed. even though ce# may be low throughout these extended data transfer cycles, the memory device host interface will go to the automatic sleep current at t acc + 30 ns. the device will remain at the automatic sleep current for t assb . then the device will transition to the standby current level. this keeps the memory at the automatic sleep or standby power level for most of the long duration data transfer cycles, rather than consuming full read power all the time that the memory device is selected by the host system. however, the eac operates independent of the automatic sleep mode of the host interface and will continue to draw current during an active embedded algorithm. only when both the host interface and eac are in their standby states is the standby level current achieved. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 43 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 8 4 read 8.4.1 read with output disable when the ce# signal is asserted low, the host system memory controller begins a read or write data transfer. often there is a period at the beginning of a data transfer when ce# is low, address is valid, oe# is high, and we# is high. during this state a read access is assumed and the random read process is started while the data outputs remain at high impedance. if the oe# signal goes low, the interface transitions to the random read state, with data outputs actively driven. if the we# signal is asserted low, the interface transitions to the write state. note, oe# and we# should never be low at the same time to ensure no data bus contention between the host system and memory. 8.4.2 random (asynchronous) read when the host system interface selects the memory device by driving ce# low, the device interface leaves the standby state. if we# is high when ce# goes low, a random read access is started. the data output depends on the address map mode and the address provided at the time the read access is started. the data appears on dq15-dq0 when ce# is low, oe# is low, we# remains high, address remains stable, and the asynchronous access times are satisfed. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable ce# to valid data at the outputs. in order for the read data to be driven on to the data outputs the oe# signal must be low at least the output enable time (t oe ) before valid data is available. at the completion of the random access time from ce# active (t ce ), address stable (t acc ), or oe# active (t oe ), whichever occurs latest, the data outputs will provide valid read data from the currently active address map mode. if ce# remains low and any of the a max to a4 address signals change to a new value, a new random read access begins. if ce# remains low and oe# goes high the interface transitions to the read with output disable state. if ce# remains low, oe# goes high, and we# goes low, the interface transitions to the write state. if ce# returns high, the interface goes to the standby state. back to back accesses, in which ce# remains low between accesses, requires an address change to initiate the second access. see section 10.3.1: asynchronous read operations (page 54 ) . 8.4.3 page read after a random read access is completed, if ce# remains low, oe# remains low, the a max to a4 address signals remain stable, and any of the a3 to a0 address signals change, a new access within the same page begins. the page read completes much faster (t pacc ) than a random read access. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 44 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 8.4.4 asynchronous write when we# goes low after ce is low, there is a transition from one of the read states to the write state. if we# is low before ce# goes low, there is a transition from the standby state directly to the write state without beginning a read access. when ce# is low, oe# is high, and we# goes low, a write data transfer begins. note, oe# and we# should never be low at the same time to ensure no data bus contention between the host system and memory. when the asynchronous write cycle timing requirements are met the we# can go high to capture the address and data values in to eac command memory. address is captured by the falling edge of we# or ce#, whichever occurs later. data is captured by the rising edge of we# or ce#, whichever occurs earlier. when ce# is low before we# goes low and stays low after we# goes high, the access is called a we# controlled write. when we# is high and ce# goes high, there is a transition to the standby state. if ce# remains low and we# goes high, there is a transition to the read with output disable state. when we# is low before ce# goes low and remains low after ce# goes high, the access is called a ce# controlled write. a ce# controlled write transitions to the standby state. if we# is low before ce# goes low, the write transfer is started by ce# going low. if we# is low after ce# goes high, the address and data are captured by the rising edge of ce#. these cases are referred to as ce# controlled write state transitions. write followed by read accesses, in which ce# remains low between accesses, requires an address change to initiate the following read access. back to back accesses, in which ce# remains low between accesses, requires an address change to initiate the second access. the eac command memory array is not readable by the host system and has no aso. the eac examines the address and data in each write transfer to determine if the write is part of a legal command sequence. when a legal command sequence is complete the eac will initiate the appropriate ea. 8.4.5 write pulse glitch protection noise pulses of less than 5 ns (typical) on we# will not initiate a write cycle. 8.4.6 logical inhibit write cycles are inhibited by holding oe# at v il , or ce# at v ih , or we# at v ih . to initiate a write cycle, ce# and we# must be low (v il ) while oe# is high (v ih ). *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 45 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 9 electrical specifcations 9 1 absolute maximum ratings table 16: absolute maximum ratings storage temperature plastic packages -65c to +150c ambient temperature with power applied -65c to +125c voltage with respect to ground all pins other than reset# 1 -0.5v to (v io + 0.5v) reset# 1 -0.5v to (v cc + 0.5v) output short circuit current 2 100 ma v cc -0.5v to +4.0v v io notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 5 (page 48 ) . maximum dc voltage on input or i/o pins is v cc +0.5v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0v for periods up to 20 ns. see figure 6 (page 48 ) . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 9 2 latchup characteristics this product complies with jedec standard jesd78c latchup testing requirements. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 46 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 9 3 operating ranges 9.3.1 temperature ranges industrial (i) devices ambient temperature (t a ) -40c to +85c 9.3.2 power supply voltages v cc 2.7v to 3.6v v io 1.65v to v cc + 200 mv operating ranges defne those limits between which the functionality of the device is guaranteed. 9.3.3 power-up and power-down during power-up or power-down v cc must always be greater than or equal to v io (v cc v io ). the device ignores all inputs until a time delay of t vcs has elapsed after the moment that v cc and v io both rise above, and stay above, the minimum v cc and v io thresholds. during t vcs the device is performing power on reset operations. during power-down or voltage drops below v cc lockout maximum (v lko ), the v cc and v io voltages must drop below v cc reset (v rst ) minimum for a period of t pd for the part to initialize correctly when v cc and v io again rise to their operating ranges. see figure 4: power-down and voltage drop (page 47 ) . if during a voltage drop the v cc stays above v lko maximum the part will stay initialized and will work correctly when v cc is again above v cc minimum. if the part locks up from improper initialization, a hardware reset can be used to initialize the part correctly. normal precautions must be taken for supply decoupling to stabilize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a suitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 f). at no time should v io be greater then 200 mv above v cc (v cc v io - 200 mv). *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 47 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 17: power-up/power-down voltage and timing symbol parameter min max unit v cc v cc power supply 2.7 3.6 v v lko v cc level below which re-initialization is required 1 2.25 2.5 v v rst v cc and v io low voltage needed to ensure initialization will occur 1 1.0 v t vcs v cc and v io minimum to frst access 1 300 s t pd duration of v cc v rst (min) 1 15 s note: 1. not 100% tested. figure 3: power-up 72 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet note: 1. not 100% tested. figure 9.1 power-up figure 9.2 power-down and voltage drop table 9.2 power-up/power-down voltage and timing symbol parameter min max unit v cc v cc power supply 2.7 3.6 v v lko v cc level below which re-initialization is required (note 1) 2.25 2.5 v v rst v cc and v io low voltage needed to ensure initialization will occur (note 1) 1.0 v t vcs v cc and v io vcc (max) vcc (m in) power supply voltage tim e t vcs full device access vcc v io (m in) v io (max) v io v cc (max) v cc (m in) v cc and v io tim e v rst (m in) t pd t vcs no device access allowed full device access allowed v lko (max) figure 4: power-down and voltage drop 72 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet note: 1. not 100% tested. figure 9.1 power-up figure 9.2 power-down and voltage drop table 9.2 power-up/power-down voltage and timing symbol parameter min max unit v cc v cc power supply 2.7 3.6 v v lko v cc level below which re-initialization is required (note 1) 2.25 2.5 v v rst v cc and v io low voltage needed to ensure initialization will occur (note 1) 1.0 v t vcs v cc and v io vcc (max) vcc (m in) power supply voltage tim e t vcs full device access vcc v io (m in) v io (max) v io v cc (max) v cc (m in) v cc and v io tim e v rst (m in) t pd t vcs no device access allowed full device access allowed v lko (max) *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 48 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 9.3.4 input signal overshoot figure 5: maximum negative overshoot waveform october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 73 data sheet 9.3.4 input si gnal overshoot figure 9.3 maximum negative overshoot waveform figure 9.4 maximum positive overshoot waveform 20 n s 20 n s 20 n s ?2 .0 v v m a x il v min il 20 ns 20 ns 20 ns v io + 2.0 v v m a x ih v min ih figure 6: maximum positive overshoot waveform october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 73 data sheet 9.3.4 input si gnal overshoot figure 9.3 maximum negative overshoot waveform figure 9.4 maximum positive overshoot waveform 20 n s 20 n s 20 n s ?2 .0 v v m a x il v min il 20 ns 20 ns 20 ns v io + 2.0 v v m a x ih v min ih 9 4 dc characteristics table 18: dc characteristics (-40c to +85c) parameter description test conditions min typ 2 max unit v ss input load current v in = v ss to v cc , v cc = v cc max +0.02 1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max +0.02 1.0 a i cc1 v cc active read current ce# = v il , oe# = v ih , address switching@ 5 mhz, v cc = v cc max 55 60 ma i cc2 v cc intra-page read current ce# = v il , oe# = v ih , address switching@ 33 mhz, v cc = v cc max 9 25 ma i cc3 v cc active erase/program current 1,2 ce# = v il , oe# = v ih , v cc = v cc max 45 100 ma i cc4 v cc standby current ce#, reset#, oe# = v ih , v ih = v io v il = v ss , v cc = v cc max 70 100 a *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 49 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* parameter description test conditions min typ 2 max unit i cc5 v cc reset current 2,7 ce# = v ih , reset# = v il , v cc = v cc max 10 20 ma i cc6 automatic sleep mode 3 v ih = v io , v il = v ss , v cc = v cc max, t acc + 30 ns 3 6 ma v ih = v io , v il = v ss , v cc = v cc max, t assb 100 150 a i cc7 v cc current during power up 2,6 reset# = v io , ce# = v io , oe# = v io , v cc = v cc max, 53 80 ma v il input low voltage 4 -0.5 0.3 x v io v v ih input high voltage 4 0.7 x v io v io + 0.4 v v ol output low voltage 4,8 i ol = 100 a for dq15-dq0; iol = 2 ma for ry/by# 0.15 x v io v v oh output high voltage 4 i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage 2 2.25 2.5 v v rst low v cc power on reset voltage 2 1.0 v notes: 1. i cc active while embedded algorithm is in progress. 2. not 100% tested. 3. automatic sleep mode enables the lower power mode when addresses remain stable for the specifed designated time. 4. v io = 1.65v to v cc or 2.7v to v cc depending on the model. 5. v cc = 3v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at >1.8v. 6. during power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part initializes correctly. 7. if an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specifcation until the embedded operation is stopped by the reset. if no embedded operation is in progress when reset is started, or following the stopping of an embedded operation, i cc5 will be drawn during the remainder of t rph . after the end of t rph the device will go to standby mode until the next read or write. 8. the recommended pull-up resistor for ry/by# output is 5k to 10k ohms. table 18: dc characteristics (-40c to +85c) (continued) *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 50 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 9 5 capacitance characteristics table 19: connector capacitance for fbga (lae) package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 7 8 pf c out output capacitance v out = 0 5 6 pf c in2 control pin capacitance v in = 0 3 7 pf ry/by# output capacitance v out = 0 3 4 pf notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. 10 timing specifcations 10 1 ac test conditions figure 7: test setup october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 77 data sheet 10. timing specifications 10.1 key to switching waveforms 10.2 ac test conditions figure 10.1 test setup note: 1. measured between v il max and v ih min. figure 10.2 input waveforms and measurement levels waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state (high-z) table 10.1 test specification parameter all speeds units output load capacitance, c l 30 pf input rise and fall times (note 1) 1.5 ns input pulse levels 0.0-v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v c l device under te s t v io 0.0 v 0.5 v io 0.5 v io output measurement level input *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 51 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 20: test specifcation parameter all speeds units output load capacitance, cl 30 pf input rise and fall times 1 1.5 ns input pulse levels 0.0-v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v note: 1. measured between v il max and v ih min. figure 8: input waveforms and measurement levels october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 77 data sheet 10. timing specifications 10.1 key to switching waveforms 10.2 ac test conditions figure 10.1 test setup note: 1. measured between v il max and v ih min. figure 10.2 input waveforms and measurement levels waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state (high-z) table 10.1 test specification parameter all speeds units output load capacitance, c l 30 pf input rise and fall times (note 1) 1.5 ns input pulse levels 0.0-v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v c l device under te s t v io 0.0 v 0.5 v io 0.5 v io output measurement level input 10.2 power-on reset (por) and warm reset normal precautions must be taken for supply decoupling to stabilize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a suitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 f). table 21: power on and reset parameters parameter description limit value unit t vcs v cc setup time to frst access 1,2 min 300 s t vios v io setup time to frst access 1,2 min 300 s t rph reset# low to ce# low min 35 s t rp reset# pulse width min 200 ns t rh time between reset# (high) and ce# (low) min 50 ns t ceh ce# pulse width high min 20 ns *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 52 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 21: power on and reset parameters (continued) notes: 1. not 100% tested. 2. timing measured from v cc reaching v cc minimum and v io reaching v io minimum to v ih on reset and v il on ce#. 3. reset# low is optional during por. if reset is asserted during por, the later of t rph , t vios , or t vcs will determine when ce# may go low. if reset# remains low after t vios , or t vcs is satisfed, t rph is measured from the end of t vios , or t vcs . reset must also be high t rh before ce# goes low. 4. v cc v io - 200 mv during power-up. 5. v cc and v io ramp rate can be non-linear. 6. sum of t rp and t rh must be equal to or greater than t rph . 10.2.1 power-on (cold) reset (por) during the rise of power supplies the v io supply voltage must remain less than or equal to the v cc supply voltage. v ih also must remain less than or equal to the v io supply. the cold reset embedded algorithm requires a relatively long, hundreds of s, period (t vcs ) to load all of the eac algorithms and default state from non-volatile memory. during the cold reset period all control signals including ce# and reset# are ignored. if ce# is low during t vcs the device may draw higher than normal por current during t vcs but the level of ce# will not affect the cold reset ea. ce# or oe# must transition from high to low after t vcs for a valid read or write operation. reset# may be high or low during t vcs . if reset# is low during t vcs it may remain low at the end of t vcs to hold the device in the hardware reset state. if reset# is high at the end of t vcs the device will go to the standby state. when power is frst applied, with supply voltage below v rst then rising to reach operating range minimum, internal device confguration and warm reset activities are initiated. ce# is ignored for the duration of the por operation (t vcs or t vios ). reset# low during this por period is optional. if reset# is driven low during por it must satisfy the hardware reset parameters t rp and t rph . in which case the reset operations will be completed at the later of t vcs or t vios or t rph . during cold reset the device will draw i cc7 current. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 53 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 9: power-up diagram 78 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet 10.3 power-on reset (por) and warm reset normal precautions must be taken for supply decoupling to stabilize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a suitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 f). notes: 1. not 100% tested. 2. timing measured from v cc reaching v cc minimum and v io reaching v io minimum to v ih on reset and v il on ce#. 3. reset# low is optional during por. if reset is asserted during por, the later of t rph , t vios , or t vcs will determine when ce# may go low. if reset# remains low after t vios , or t vcs is satisfied, t rph is measured from the end of t vios , or t vcs . reset must also be high t rh before ce# goes low. 4. v cc v io - 200 mv during power-up. 5. v cc and v io ramp rate can be non-linear. 6. sum of t rp and t rh must be equal to or greater than t rph. 10.3.1 power-on (cold) reset (por) during the rise of power supplies the v io supply voltage must remain less than or equal to the v cc supply voltage. v ih also must remain less than or equal to the v io supply. the cold reset embedded algorithm requires a relatively long, hundreds of s, period (t vcs ) to load all of the eac algorithms and default state from non-volatile me mory. during the cold reset period all control signals including ce# and reset# are ignored. if ce# is low during t vcs the device may draw higher than normal por current during t vcs but the level of ce# will not affect the cold reset ea. ce# or oe# must transition from high to low after t vcs for a valid read or write operation. reset# may be high or low during t vcs . if reset# is low during t vcs it may remain low at the end of t vcs to hold the device in the hardware reset state. if reset # is high at the end of t vcs the device will go to the standby state. when power is first applied, with supply voltage below v rst then rising to reach operating range minimum, internal device configuration and warm reset activities ar e initiated. ce# is ignored for the duration of the por operation (t vcs or t vios ). reset# low during this por period is opt ional. if reset# is driven low during por it must satisfy the hardware reset parameters t rp and t rph . in which case the reset operations will be completed at the later of t vcs or t vios or t rph . during cold reset the device will draw i cc7 current. figure 10.3 power-up diagram table 10.2 power on and reset parameters parameter description limit value unit t vcs v cc setup time to first access (notes 1 , 2 ) min 300 s t vios v io setup time to first access (notes 1 , 2 ) min 300 s t rph reset# low to ce# low min 35 s t rp reset# pulse width min 200 ns t rh time between reset# (high) and ce# (low) min 50 ns t ceh ce# pulse width high min 20 ns vcc vio reset# ce# trh tvios tvcs tceh 10.2.2 hardware (warm) reset during hardware reset (t rph ) the device will draw icc5 current. when reset# continues to be held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. if a cold reset has not been completed by the device when reset# is asserted low after t vcs , the cold reset# ea will be performed instead of the warm reset#, requiring t vcs time to complete. see figure 10: hardware reset (page 54 ) . after the device has completed por and entered the standby state, any later transition to the hardware reset state will initiate the warm reset embedded algorithm. a warm reset is much shorter than a cold reset, taking tens of s (t rph ) to complete. during the warm reset ea, any in progress embedded algorithm is stopped and the eac is returned to its por state without reloading eac algorithms from non-volatile memory. after the warm reset ea completes, the interface will remain in the hardware reset state if reset# remains low. when reset# returns high the interface will transit to the standby state. if reset# is high at the end of the warm reset ea, the interface will directly transit to the standby state. if por has not been properly completed by the end of t vcs , a later transition to the hardware reset state will cause a transition to the power-on reset interface state and initiate the cold reset embedded algorithm. this ensures the device can complete a cold reset even if some aspect of the system power-on voltage ramp-up causes the por to not initiate or complete correctly. the ry/by# pin is low during cold or warm reset as an indication that the device is busy performing reset operations. hardware reset is initiated by the reset# signal going to v il . *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 54 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 10: hardware reset october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 79 data sheet 10.3.2 hardware (warm) reset during hardware reset (t rph ) the device will draw i cc5 current. when reset# continues to be held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. if a cold reset has not been completed by the device when reset# is asserted low after t vcs , the cold reset# ea will be performed instead of the warm reset#, requiring t vcs time to complete. see figure 10.4, hardware reset on page 79 . after the device has completed por and entered the st andby state, any later transition to the hardware reset state will initiate the warm reset embedded algo rithm. a warm reset is much shorter than a cold reset, taking tens of s (t rph ) to complete. during the warm reset ea, any in progress embedded algorithm is stopped and the eac is returned to its por stat e without reloading eac algorithms from non-volatile memory. after the warm reset ea completes, the inte rface will remain in the hardware reset state if reset# remains low. when reset# returns high the inte rface will transit to the standby state. if reset# is high at the end of the warm reset ea, the inte rface will directly transit to the standby state. if por has not been properly completed by the end of t vcs , a later transition to the hardware reset state will cause a transition to the power-on reset interface st ate and initiate the cold reset embedded algorithm. this ensures the device can complete a cold reset even if some aspect of the system power-on voltage ramp-up causes the por to not initiate or complete correctly. the ry/by# pin is low during cold or warm reset as an indication that the device is busy performing reset operations. hardware reset is in itiated by the reset# signal going to v il . figure 10.4 hardware reset reset# ce# trp trph trh tceh 10 3 ac characteristics 10.3.1 asynchronous read operations table 22: read operation v io = v cc = 2.7v to 3.6v (-40c to +85c) parameter description test setup speed option unit jedec std 90 100 110 t avav t rc read cycle time 1 128 mb 256 mb min 90 100 ns 512 mb 1 gb 100 110 t avqv t acc address to output delay ce# = v il oe# = v 128 mb 256 mb max 90 100 ns 512 mb 1 gb 100 110 t elqv t ce chip enable to output delay oe# = v il 128 mb 256 mb max 90 100 ns 512 mb 1 gb 100 110 t pacc page access time 128 mb 256 mb max 15 20 ns 512 mb 1 gb 15 20 t glqv t oe output enable to output delay max 25 ns t axqx t oh output hold time from addresses ce# or oe# whichever occurs first min 0 ns t ehq t df chip enable or output enable to output high- 1 max 15 ns t oeh output enable hold time 1 read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time 1 ce# = v il address stable typ 5 s max 8 s note: 1. not 100% tested. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 55 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 23: read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v (-40c to +85c) parameter description test setup speed option unit jedec std 90 100 110 t avav t rc read cycle time 1 128 mb, 256 mb min 100 110 ns 512 mb, 1 gb 110 120 t avqv t acc address to output delay ce# = v il oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t elqv t ce chip enable to output delay oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t pacc page access time 128 mb, 256 mb max 25 30 ns 512 mb, 1 gb 25 30 t glqv t oe output enable to output delay max 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high-z 1 max 20 ns t oeh output enable hold time 1 read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time 1 ce# = v il , address stable typ 5 s max 8 s note: 1. not 100% tested. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 56 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 11: back to back read (t acc ) operation timing diagram 82 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet figure 10.5 back to back read (t acc ) operation timing diagram figure 10.6 back to back read operation (t rc )timing diagram note: back to back operations, in which ce# remains low between accesses, requires an address change to initiate the second access. figure 10.7 page read timing diagram note: word configuration: toggle a0, a1, a2, and a3. amax-a0 ce# oe# dq15-dq0 tacc toe tce tdf tdf toh toh toh amax-a0 ce# oe# dq15-dq0 trc tacc toe tce tdf toh toh amax-a4 a3-a0 ce# oe# dq15-dq0 tacc toe tce tpacc figure 12: back to back read operation (t rc )timing diagram 82 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet figure 10.5 back to back read (t acc ) operation timing diagram figure 10.6 back to back read operation (t rc )timing diagram note: back to back operations, in which ce# remains low between accesses, requires an address change to initiate the second access. figure 10.7 page read timing diagram note: word configuration: toggle a0, a1, a2, and a3. amax-a0 ce# oe# dq15-dq0 tacc toe tce tdf tdf toh toh toh amax-a0 ce# oe# dq15-dq0 trc tacc toe tce tdf toh toh amax-a4 a3-a0 ce# oe# dq15-dq0 tacc toe tce tpacc note: back to back operations, in which ce# remains low between accesses, requires an address change to initiate the second access. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 57 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 13: page read timing diagram 82 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet figure 10.5 back to back read (t acc ) operation timing diagram figure 10.6 back to back read operation (t rc )timing diagram note: back to back operations, in which ce# remains low between accesses, requires an address change to initiate the second access. figure 10.7 page read timing diagram note: word configuration: toggle a0, a1, a2, and a3. amax-a0 ce# oe# dq15-dq0 tacc toe tce tdf tdf toh toh toh amax-a0 ce# oe# dq15-dq0 trc tacc toe tce tdf toh toh amax-a4 a3-a0 ce# oe# dq15-dq0 tacc toe tce tpacc note: word confguration: toggle a0, a1, a2, and a3. 10.3.2 asynchronous write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time 1 min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling or following status register read. min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp we# pulse width min 25 ns t whwl t wph we# pulse width high min 20 ns note: 1. not 100% tested. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 58 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 24: back to back write operation timing diagram october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 83 data sheet 10.4.2 asynchronous write operations note: 1. not 100% tested. figure 10.8 back to back write operation timing diagram table 10.7 write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling or following status register read. min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp we# pulse width min 25 ns t whwl t wph we# pulse width high min 20 ns amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc t cs tch figure 14: back to back (ce#v il ) write operation timing diagram 84 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet figure 10.9 back to back (ce#vil) write operation timing diagram figure 10.10 write to read (t acc ) operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc tcs amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tdf tdf toh toh toh tas tah tds tdh twp tcs tsr_w *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 59 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 15: write to read (t acc ) operation timing diagram 84 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet figure 10.9 back to back (ce#vil) write operation timing diagram figure 10.10 write to read (t acc ) operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc tcs amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tdf tdf toh toh toh tas tah tds tdh twp tcs tsr_w figure 16: write to read (t ce ) operation timing diagram october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 85 data sheet figure 10.11 write to read (t ce ) operation timing diagram figure 10.12 read to write (ce# v il ) operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tce tdf tdf toh toh toh tas tah tds tdh twp tcs tch tsr_w amax-a0 ce# oe# we# dq15-dq0 tas tds tah tdh tch tacc tce toe toh toh tdf twp tghwl *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 60 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 17: read to write (ce# v il ) operation timing diagram october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 85 data sheet figure 10.11 write to read (t ce ) operation timing diagram figure 10.12 read to write (ce# v il ) operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tce tdf tdf toh toh toh tas tah tds tdh twp tcs tch tsr_w amax-a0 ce# oe# we# dq15-dq0 tas tds tah tdh tch tacc tce toe toh toh tdf twp tghwl figure 18: read to write (ce# toggle) operation timing diagram 86 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet figure 10.13 read to write (ce# toggle) operation timing diagram notes: 1. not 100% tested. 2. upon the rising edge of we#, must wait t sr/w before switching to another address. 3. see table 5.4 on page 46 and table 5.5 on page 47 for specific values. table 10.8 erase/program operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t whwh1 t whwh1 write buffer program operation ty p (note 3) s effective write buffer program operation per word ty p (note 3) s program operation per word or page ty p (note 3) s t whwh2 t whwh2 sector erase operation (note 1) ty p (note 3) ms t busy erase/program valid to ry/by# delay max 80 ns t sr/w latency between read and write operations (note 2) min 10 ns t esl erase suspend latency max (note 3) s t psl program suspend latency max (note 3) s t rb ry/by# recovery time min 0 s amax-a0 ce# oe# we# dq15-dq0 tacc toe tce tas tcs tds tah tdh twp tch toh toh toh tdf tdf tghwl *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 61 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* table 25: erase/program operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t whwh1 t whwh1 write buffer program operation typ note 3 s effective write buffer program operation per word typ note 3 s program operation per word or page typ note 3 s t whwh2 t whwh2 sector erase operation 1 typ note 3 ms t busy erase/program valid to ry/by# delay max 80 ns t sr/w latency between read and write operations 2 min 10 ns t esl erase suspend latency max note 3 s t psl program suspend latency max note 3 s t rb ry/by# recovery time min 0 s notes: 1. not 100% tested. 2. upon the rising edge of we#, must wait t sr/w before switching to another address. 3. see table 6: embedded algorithm characteristics (-40c to +85c) (page 27 ) for specifc values. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 62 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 19: program operation timing diagram october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 87 data sheet figure 10.14 program operation timing diagram note: 1. pa = program address, pd = program data, d out is the true data at the program address. figure 10.15 chip/sector erase operation timing diagram note: 1. sa = sector address (for sector erase), va = valid address for reading status data. oe# we# ce# data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph 555h pa pa read status data (las t two cycles) a0h t cs status d out progr am command sequence (las t two cycles) ry/by# t rb t bu sy t ch pa oe# ce# addresses we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase t ds t cs t dh t ch t whwh2 va va erase command sequence (last two cycles) read status data (last two cycles) ry/by# t rb t busy 30h in progress complete 55h note: 1. pa = program address, pd = program data, d out is the true data at the program address. figure 20: chip/sector erase operation timing diagram october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 87 data sheet figure 10.14 program operation timing diagram note: 1. pa = program address, pd = program data, d out is the true data at the program address. figure 10.15 chip/sector erase operation timing diagram note: 1. sa = sector address (for sector erase), va = valid address for reading status data. oe# we# ce# data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph 555h pa pa read status data (las t two cycles) a0h t cs status d out progr am command sequence (las t two cycles) ry/by# t rb t bu sy t ch pa oe# ce# addresses we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase t ds t cs t dh t ch t whwh2 va va erase command sequence (last two cycles) read status data (last two cycles) ry/by# t rb t busy 30h in progress complete 55h note: 1. sa = sector address (for sector erase), va = valid address for reading status data. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 63 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 10.3.3 alternate ce# controlled write operations table 26: alternate ce# controlled write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time 1 min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t 0eph oe# high during toggle bit polling min 20 ns t ghek t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t elwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 ns t ehel t cph ce# pulse width high min 20 ns note: 1. not 100% tested. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 64 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* figure 21: back to back (ce#) write operation timing diagram october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 89 data sheet 10.4.3 alternate ce# contro lled write operations note: 1. not 100% tested. figure 10.19 back to back (ce#) write operation timing diagram table 10.9 alternate ce# controlled write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t 0eph oe# high during toggle bit polling min 20 ns t ghek t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t elwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 ns t ehel t cph ce# pulse width high min 20 ns amax-a0 ce# oe# we# dq15-dq0 tds tdh tas tah twc tcp tcph tws twh figure 22: (ce#) write to read operation timing diagram 90 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet figure 10.20 (ce#) write to read operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tacc toe tce tdf toh twc tas tah tds tdh tws twh toeh *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 65 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 11 physical interface 11 1 connection diagram figure 23: 64-ball fortifed ball grid array - product pinout (top view) october 9, 2013 s29gl_128s_01gs_00_08 gl-s mirrorbit ? family 93 data sheet 11.2 64-ball fbga 11.2.1 connection diagram figure 11.3 64-ball fortified ball grid array notes: 1. ball e1, do not use (dnu), a device internal signal is conne cted to the package connector. the connector may be used by spans ion for test or other purposes and is not intended for connection to any host system signal. do not use these connections for pcb signa l routing channels. though not recommended, the ball can be connected to v cc or v ss through a series resistor. 2. balls f7 and g1, reserved for future use (rfu). 3. balls a1, a8, c1, d1, h1, and h8, no connect (nc). abcd efgh 8 nc a2 2 a2 3 vio v ss a2 4 a25 nc 7 a1 3 a12 a14 a15 a16 rfu dq15 v ss 6 a9 a 8 a10 a11 dq7 dq14 dq1 3 dq6 5 we# re s et# a21 a19 dq5 dq12 vcc dq4 4 ry/by# wp# a1 8 a20 dq2 dq10 dq11 dq 3 3 a7 a1 7 a6 a5 dq0 dq 8 dq9 dq1 2 a 3 a4 a2 a1 a0 ce# oe# v ss 1 nc dnu vio rfu nc top view product pino u t - nc for gl128s nc for gl512s , gl256s , gl128s nc for gl256s , gl128s nc nc nc notes: 1. ball e1, do not use (dnu), a device internal signal is connected to the package connector. the connector may be used by the ocm for test or other purposes and is not intended for connection to any host system signal. do not use these connections for pcb signal routing channels. though not recommended, the ball can be connected to v cc or v ss through a series resistor. 2. balls f7 and g1, reserved for future use (rfu). 3. balls a1, a8, c1, d1, h1, and h8, no connect (nc). *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 66 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 11 2 physical diagram C lae064 figure 24: lae064 - 64-ball fortifed ball grid array (fbga), 9 x 9 mm 94 gl-s mirrorbit ? family s29gl_128s_01gs_00_08 october 9, 2013 data sheet 11.2.2 physical diagram ? lae064 figure 11.4 lae064?64-ball fortified ball grid array (fbga), 9 x 9 mm package lae 064 jedec n/a 9.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 9.00 bsc. body size e 9.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement ? none depopulated solder balls 3623 \ 16-038.12 \ 1.16.07 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010? except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in ? the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 67 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* 12 ordering information table 27: ordering information part number device grade MYX29GL01GS11DPIV2bg-itrl industrial for more information, contact a micross sales representative at sales@micross.com . *advanced information. subject to change without notice. form #: csi-d-685 document 001
MYX29GL01GS11DPIV2 revision 1.0 - 01/26/2015 68 1gb gl-s mirrorbit ? eclipse ? flash memory MYX29GL01GS11DPIV2* document title 1gbit - 64m x 16 gl-s mirrorbit ? eclipse? flash memory revision history revision # history release date status 1.0 initial release january 23, 2015 preliminary *advanced information. subject to change without notice. form #: csi-d-685 document 001

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